An integrated circuit may include a pre-metal dielectric (PMD) layer and an inter-level dielectric (ILD) layer between a semiconductor substrate and a first metal interconnect level. Upper components, such as ferroelectric capacitors, may be formed between the PMD layer and the ILD layer. Contacts between lower components in and on the substrate and the first metal interconnect level may be stacked contacts including a lower contact lower contact formed in the PMD layer and an upper contact formed in the ILD layer. The lower contact and the upper contact may be formed by depositing contact metal in contact holes and over top surfaces of the PMD layer and ILD layer, respectively, and subsequently removing the contact metal over the top surfaces of the PMD layer and ILD layer, leaving the lower contact and the upper contact, respectively. Such a process limits the width of the lower contact and the upper contact, so that forming a low resistance stacked contact may be problematic.